The invention relates generally to integrated circuits and more particularly to the use of amorphous ternary aluminum nitride and boride alloy materials for diffusion barrier layers in such circuits.
In semiconductor devices, it is common for the design to require interfaces of silicon and a metal such as aluminum or tungsten. For example, aluminum and tungsten are commonly used as the material of choice for electrical contacts, which contacts interface with electrically active areas made of doped silicon. It is also common in the fabrication of semiconductor devices to anneal the devices at elevated temperatures, such as 500xc2x0 C. At these temperatures, the metal and silicon will rapidly interdifflise into each other at the interface. Even at room temperature, the metal and silicon will interdiffuse over time. Such interdiffusion changes the semiconductive properties of the silicon and causes defective devices.
Capacitors are used in a wide variety of integrated circuits and present special interdiffusion concerns. Capacitors are of particular concern in DRAM (dynamic random access memory) circuits. The electrodes in a DRAM cell capacitor must protect the dielectric film (e.g., Ta2O5 and (Ba,Sr)TiO3) from interaction with surrounding materials and from the harsh thermal processing encountered in subsequent steps of DRAM process flow. In order to function well as a bottom electrode, the electrode film or film stack must act as an effective barrier to the diffusion of oxygen and silicon. Oxidation of the underlying Si results in decreased series capacitance, thus degrading the capacitor.
It is common practice to provide diffusion barriers in semiconductor devices. A thin film of titanium nitride (TiN) or titanium tungsten (TiW) is conventionally used as diffusion barrier. Conventional barrier materials, however, tend to be polycrystalfine with grain boundaries through which diffusion of Si and O atomic species can occur.
The conventional diffusion barriers for silicon/metal interfaces and capacitor dielectrics, while generally relatively effective at room temperature, can fail at more elevated temperatures. Many preferred semiconductor fabrication processes, such as deposition, reflow, and annealing, require elevated temperatures. Thus conventional diffusion barriers can create limits on the processes that can be used to fabricate a semiconductor device. There is a need for a diffusion barrier that is more effective than conventional polycrystalline barriers, especially at elevated temperatures.
What is needed are improved diffusion barrier layers and fabrication methods that offer a combination of good conformality, high conductivity, and excellent barrier properties for protecting against interdiffusion at capacitor dielectrics and silicon/metal interfaces in semiconductor devices, particularly during high temperature fabrication processes.
The present invention provides mixed-metal nitride, boride and boride-nitride alloy barrier layers of the formula MxAlyNzBw, wherein M is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, or W; x is greater than zero; y is greater than or equal to zero; the sum of z and w is greater than zero; and wherein when y is zero, z and w are both greater than zero, and when M is Ti, w is greater than 0.
The preferred metals (M) are Ti, Zr, Hf, Ta, Nb, Mo and W. Preferably, when M is Ti, Zr, Hf, Ta, or Nb, x+y=1, and z+w/2=1; and when M is Mo or W, x+y=1, and z+2w=1. Most preferably, M is Ti, Zr, Hf, Ta, or Nb and MxAlyNzBw has the formula M0.7A0.3N0.3B1.4, or M is Mo, or W, and MxAlyNzBw has the formula M0.7Al0.3N0.3B0.35.
The invention also provides semiconductor capacitors fabricating capacitors and other devices containing MxAlyNzBw barrier layers in order to protect capacitor cell dielectrics, such as SiO2, Ta2O5, SrTiO3 (xe2x80x9cSTxe2x80x9d), (Ba,Sr)TiO3 (xe2x80x9cBSTxe2x80x9d), Pb(Z,Ti)O3 (xe2x80x9cPZTxe2x80x9d),SrBi2Ta2O9(xe2x80x9cSBTxe2x80x9d) and Ba(Zr,Ti)O3 (xe2x80x9cBZTxe2x80x9d).
The mixed-metal nitride and boride layers of the invention provide excellent barrier protection, conductivity as capacitor electrodes, and conformality, and so may be employed either as capacitor electrodes, or as separate barrier layers formed adjacent to conventional capacitor electrodes, either atop these electrodes or interposed between the electrode and the capacitor dielectric. Preferably, the MxAlyNzBw layer according to the invention comprises a thin barrier film between a cell dielectric and an underlying polysilicon (poly) plug or drain in a DRAM cell array, as well as acting as a lower electrode.
The barrier layers and methods of the invention are also useful in any device containing a Si/metal interface, and any other semiconductor device where protection against degradation through diffusion and thermal effects is desired.